The present invention relates to solid-state imaging apparatus that are used for example in digital cameras and digital video cameras.
There are two read methods in MOS-type solid-state imaging apparatus, namely, the method of reading light signal with using a rolling shutter function where signal accumulation of photoelectric conversion section is started/ended row by row, and the method of reading light signal with using a global shutter function where signal accumulation of the photoelectric conversion section is started/ended simultaneously of all pixels. These methods have both merits and demerits, and imaging apparatus where switching is made between the above described read functions depending on photographing conditions to obtain better results have been proposed for example in Japanese Patent Application Laid-Open 2000-320141.
FIG. 1 is a block diagram schematically showing a fundamental construction of prior-art solid-state imaging apparatus. The construction of this example includes at least: a pixel array 1 consisting of a plurality of pixels for receiving light and outputting signal; a vertical scanning circuit 2 for controlling the pixel array 1; a noise suppressing circuit 4 for processing and retaining signal outputted from pixel; and a horizontal scanning circuit 5. It should be noted that, in FIG. 1, numeral 6 denotes an output amplifier connected to an output signal line from the noise suppressing circuit 4. FIG. 2 is a circuit diagram showing an actual construction of the prior-art solid-state imaging apparatus; and FIG. 3 is a timing chart for explaining an operation of the noise suppressing circuit when the rolling shutter function is used. FIG. 4 is a timing chart for explaining an operation of the noise suppressing circuit when the global shutter function is used. FIG. 5 is a timing chart for explaining a light signal accumulation timing when the global shutter function is used. FIG. 6 is a timing chart for explaining a light signal accumulation timing when the rolling shutter function is used.
FIG. 2 will now be used to describe actual construction of the prior-art solid-state imaging apparatus. At first, construction of pixel will be described by way of a pixel PIX11 as an example. Those provided within the pixel PIX11 include: a photoelectric conversion section PD11; a memory (FD) C11 for accumulating signal generated at the photoelectric conversion section PD11; a transfer switch MT11 for controlling transfer from the photoelectric conversion section PD11 to the memory C11; a reset switch MR11 for resetting the memory C11; an amplification section MA11 for amplifying signal of the memory C11; and a select switch MS11 for selecting the pixel. These components are connected as shown in FIG. 2. A plurality of pixels having such construction are two-dimensionally arranged to form a pixel array 1. In this example, the pixel array 1 is shown as formed of pixels PIX11 to PIX33 that are arranged into three rows by three columns.
The transfer switch MT11 is controlled by a transfer control signal φ TR1. The reset switch MR11 is controlled by a reset control signal φ RS1. The select switch MS11 is controlled by a select control signal φ SEL1 so that the pixel signals of selected pixel row are outputted to the noise suppressing circuit 4. At the noise suppressing circuit 4, signals of value after eliminating reset variance of pixel are retained. Subsequently, the signals retained at the noise suppressing circuit 4 are read out by the horizontal scanning circuit 5 and are outputted through an output signal line and the output amplifier 6. In FIG. 2, numeral 7 denotes a pixel power supply, and I41 (I42, I43) is a biasing current supply connected to the vertical signal line.
An accumulation timing of light signal when using the rolling shutter function in thus constructed solid-state imaging apparatus will now be described by way of the timing chart shown in FIG. 6. At first, the transfer control signal φ TR1 and reset control signal φ RS1 are driven to high level to reset the photoelectric conversion section PD of the pixels of the row (first row) controlled by the two control signals φ TR1, φ RS1. Subsequently, an accumulation of light signal is started by bringing the transfer control signal φ TR1 and reset control signal φ RS1 to low level. After that, the transfer control signal φ TR2 and reset control signal φ RS2 are driven to high level to effect reset of the photoelectric conversion sections PD of the row (second row) controlled by the two control signals φ TR2, φ RS2. Subsequently, an accumulation of light signal is started by bringing the transfer control signal φ TR2 and reset control signal φ RS2 to low level.
In a similar manner, the transfer control signals and reset control signals of the rows of the third and after are driven as described so that the photoelectric conversion sections PD of each row are caused to start an accumulation of light signal. After passage of a predetermined time from the start of accumulation of light signal, pixel signals of the row controlled by the select control signal are outputted. At first, the select control signal φ SEL1 is driven to high level to select the row (first row). Next, the reset control signal φ RS1 is driven to high level to reset the memory (FD) of the pixels of the first row, and then the reset control signal φ RS1 is brought to low level to end the resetting of the memory (FD). At this time, a reset signal is outputted from the pixels of the first row. After that, the transfer control signal φ TR1 is driven to high level to transfer the light signal accumulated at the photoelectric conversion section PD of the pixels of the first row to the memory (FD), and then the transfer control signal φ TR1 is brought to low level to end the transfer. At this time, a light signal is outputted from pixel. Finally, the select control signal φ SEL1 is brought to low level to end the reading of the pixel signals of the selected first row.
Next, the row (second row) selected by the select control signal φ SEL2 is read out. This operation is similar to the operation of the first row and will not be described. In the operation using the rolling shutter function of the above, the start time and end time of accumulation of light signal are respectively different from one row to another.
An accumulation timing of light signal when using the global shutter function will now be described by way of the timing chart shown in FIG. 5. At first, the transfer control signals φ TR1, TR2, TR3, . . . , of all rows, and the reset control signals φ RS1, RS2, RS3, . . . , of all rows are simultaneously driven to high level to concurrently reset the photoelectric conversion section PD of all pixels. After that, the transfer control signals and the reset control signals are brought to low level to start accumulation of light signal. After passage of a predetermined time, the transfer control signals φ TR1, TR2, TR3, . . . , of all rows are driven to high level to transfer the light signal accumulated at the photoelectric conversion section PD to the memory (FD) concurrently of all pixels and to thereby end an accumulation of light signal.
Next, pixel signal output of the row selected by the select control signal is effected. First, the pixels of the first row are selected by driving the select control signal φ SEL1 to high level to output a light signal. Next, the reset control signal φ RS1 is driven to high level to reset the memory (FD) of the pixels of the first row, and then the reset control signal φ RS1 is brought to low level to end the resetting of the memory (FD). At this time, a reset signal is outputted from the pixels of the first row. Finally, the select control signal φ SEL1 is brought to low level to end the outputting of the pixel signals of the first row. After that, the pixel signal output of the row (second row) selected by the select control signal φ SEL2 is started. Subsequently in a similar manner, the pixel signals of the third row and after are outputted. In the operation using the global shutter function of the above, the start time and end time of light signal accumulation are the same from one row to another.
An operation of the noise suppressing circuit when using the rolling shutter function will be described below by way of the timing chart shown in FIG. 3. The operation of pixel will now be described. The select control signal φ SEL1 is driven to high level to select the row (first row) from which the pixel signals are to be read. The reset signals are read out before the reading of light signal from the photoelectric conversion section PD. In particular, the reset control signal φ RS1 is driven to high level at first to reset the memory (FD), and then the reset control signal φ RS1 is brought to low level to end the resetting of the memory (FD). A reset signal Vr of the pixel is thereby outputted to the noise suppressing circuit 4. Next, the transfer control signal φ TR1 is driven to high level to transfer the signal accumulated at the photoelectric conversion section PD to the memory (FD). A signal (Vr+Vs) where a light signal Vs is overlapped on reset signal Vr is thereby outputted from pixel to the noise suppressing circuit 4. Finally, the select control signal φ SEL1 is brought to low level to end the reading of pixel signal.
An operation of the noise suppressing circuit 4 for processing signal outputted from pixel will now be described with noticing the pixel signal of pixel PIX11. A sample-and-hold control signal φ SH and clamp control signal φ CL are driven to high level to clamp a node N2 of the noise suppressing circuit 4 by a clamping voltage (Vref) 8. At this time, the reset signal Vr is inputted to the noise suppressing circuit 4 from pixel so that the reset signal Vr is sampled by means of a clamping capacitor CCL1. Next, the clamp control signal φ CL is brought to low level to end the sampling of the reset signal Vr.
Subsequently, the signal (Vr+Vs) where the light signal Vs is overlapped on the reset signal Vr is inputted to the noise suppressing circuit 4 from the pixel. The node N2 of the noise suppressing circuit 4 at that time attains voltage GVs which is obtained by multiplication of a difference signal Vs between the previously sampled reset signal Vr and the (Vr+Vs) signal inputted from pixel by gain G to be determined by the clamping capacitor CCL1 and the sampling capacitor CSH1. Subsequently, the voltage GVs of the node N2 is retained at the sampling capacitor CSH1 by bringing the sample-and-hold control signal φ SH to low level. The gain G is expressed by the following equation.G=CCL1/(CCL1+CSH1)
By effecting the operation of the above, it is possible to output the signal GVs obtained by amplifying the light signal accumulated at the photoelectric conversion section PD.
An operation of the noise suppressing circuit 4 when using the global shutter function will be described below by way of the timing chart shown in FIG. 4. The operation of pixel will now be described. The transfer control signal φ TR1 is driven to high level so that signal accumulated at the photoelectric conversion section PD of pixel is transferred to the memory (FD). At this time, a signal obtained by overlapping the reset signal and the light signal upon each other is retained at the memory (FD).
Next, the select control signal φ SEL1 is driven to high level to select the row (first row) from which the pixel signals are to be read, and signal (Vr+Vs) where the reset signal Vr and the light signal Vs are overlapped on each other is outputted from the pixel. Subsequently, the reset control signal φ RS1 is driven to high level to reset the memory (FD). Next, the reset control signal φ RS1 is brought to low level to end the resetting of the memory (FD), and the reset signal Vr of the pixel is outputted to the noise suppressing circuit 4. Finally, the select control signal φ SEL1 is brought to low level to end the reading of the pixel signal.
An operation of the noise suppressing circuit 4 for processing signal outputted from pixel will now be described. The sample-and-hold control signal φ SH and the clamp control signal φ CL are driven to high level so that node N2 of the noise suppressing circuit 4 is clamped by means of a clamp voltage (Vref) 8. At this time, a signal (Vr+Vs) where the reset signal Vr and the light signal Vs are overlapped on each other is inputted to the noise suppressing circuit 4 from the pixel, and the overlapping signal (Vr+Vs) is sampled by means of the clamping capacitor CCL1. Next, the clamp control signal φ CL is brought to low level to end the sampling of the signal (Vr+Vs).
Subsequently, the reset signal Vr is inputted to the noise suppressing circuit 4 from the pixel. The node N2 of the noise suppressing circuit 4 at that time attains voltage −GVs which is obtained by multiplication of signal−Vs, i.e. the difference between the previously sampled signal (Vr+Vs) and the reset signal Vr inputted from the pixel by gain G to be determined by the clamping capacitor CCL1 and the sampling capacitor CSH1. Subsequently, the voltage −GVs of the node N2 is retained at the sampling capacitor CSH1 by bringing the sample-and-hold control signal φ SH to low level. By performing the above operation, it is possible to output the signal −GVs obtained by amplifying the light signal accumulated at the photoelectric conversion section PD. The light signal can be read out by performing the above operation.